This invention relates generally to controls for pipelined data processing systems. In prior art pipeline controls known to the present applicants (exemplified by systems disclosed in U.S. Pat. Nos. 3,875,391 and 4,025,771) instructions, for controlling a data processing pipeline which is time-shared by a plurality of processes in a time division multiplex mode, are shifted in bit parallel form through a register pipeline having serially coupled shift stages which are synchronized with and coupled to associated stages of the data pipeline. For a number of reasons, such systems do not efficiently adapt for: varying control activities relative to individual processes as a function of conditions occurring either externally or in the pipeline; handling many processes concurrently (e.g. more processes than the number of stages in the data pipeline); allowing for changes to be made in functions performed in response to a given instruction (which is desirable for supporting "engineering changes" at either the circuit or program level); and/or sustaining multiple different activity tasks per process (which is particularly desirable in a presently disclosed application for controlling computer I/O channels on a pipelined time division basis).